In many computer systems, there are limits to the number of bus agents that may be operably connected to the host bus if the host bus is to be clocked at a certain frequency. These limits result from the capacitance and distributed resistance physically present on chips. For example, as shown in the example prior art system of FIG. 4, in Pentium.RTM. Pro based computer systems, the host or P6 bus is limited to 4 Pentium.RTM. Pro processors and 1 bus bridge or system controller if the P6 bus is to be clocked at 100 MHz. If the P6 bus is operably connected to 4 processors and 4 system controllers, the clock rate of the P6 bus must be decreased to 66 MHz. Such a decrease in the P6 clock rate results in lower bus bandwidth and thus, a slower and relatively more inefficient computer system, having decreased system throughput. Alternatively, if added loads are desired for a computer system, these must be placed on a bus that is connected to the bus bridge, placing them a further level away from the processor. This leads to latency problems for these loads. While such problems are less of an issue in a single processor system, in systems that require multiple processors and have many attached network cards or other peripherals, the load limits represent significant obstacles or undesirable trade-offs.
Thus, there exists a need in the art for methods and apparatus for increasing the number of devices operably connected to a host bus when clocking the bus a certain frequency.